CIOMP OpenIR  > 中科院长春光机所知识产出
Ultra-high speed CameraLink image transmission based on FPGA
Sui, Y.-L.; B. He; L.-G. Zhang; W.-H. Wang and J.-N. Chen
2017
Source PublicationJilin Daxue Xuebao (Gongxueban)/Journal of Jilin University (Engineering and Technology Edition)
Volume47Issue:5
AbstractBased on Field Programmable Gate Array (FPGA), two sets of CameraLink interface transfer hardware platform are designed to compare serial-parallel converter chip and CameraLink interface based on FPGA). A new method, in which on-chip debugging tool Chipscope is combined with synchronized generation module, is proposed to detect error data accurately. The results show that CameraLink interface based on FPGA uses fewer pins with higher speed transmission rates. Single port supports a maximum transfer rate of 4.31 Gbit/s when the pixel clock is 154 MHz. The CameraLink data output can drive 6 m CameraLink transmission line, with no bit error appears for long hours, and it can be used in a variety of different systems based on CameraLink interface. 2017, Editorial Board of Jilin University. All right reserved.
Indexed Byei
Language中文
Document Type期刊论文
Identifierhttp://ir.ciomp.ac.cn/handle/181722/59199
Collection中科院长春光机所知识产出
Recommended Citation
GB/T 7714
Sui, Y.-L.,B. He,L.-G. Zhang,et al. Ultra-high speed CameraLink image transmission based on FPGA[J]. Jilin Daxue Xuebao (Gongxueban)/Journal of Jilin University (Engineering and Technology Edition),2017,47(5).
APA Sui, Y.-L.,B. He,L.-G. Zhang,&W.-H. Wang and J.-N. Chen.(2017).Ultra-high speed CameraLink image transmission based on FPGA.Jilin Daxue Xuebao (Gongxueban)/Journal of Jilin University (Engineering and Technology Edition),47(5).
MLA Sui, Y.-L.,et al."Ultra-high speed CameraLink image transmission based on FPGA".Jilin Daxue Xuebao (Gongxueban)/Journal of Jilin University (Engineering and Technology Edition) 47.5(2017).
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