Demonstration of an optoelectronic interconnect architecture for a parallel modified signed-digit adder and subtracter

	Demonstration of an optoelectronic interconnect architecture for a parallel modified signed-digit adder and subtracter
其他题名	论文其他题名
	Sun D. G.; Wang N. X.; He L. M.; Weng Z. H.; Wang D. H.; Chen R. T.
	1996
发表期刊	Optical Engineering
ISSN	0091-3286
卷号	35 期号:6 页码:1785-1793
摘要	A space-position-logic-encoding scheme is proposed and demonstrated, This encoding scheme not only makes the best use of the convenience of binary logic operation, but is also suitable for the trinary property of modified signed-digit (MSD) numbers. Based on the space-position-logic-encoding scheme, a fully parallel modified signed-digit adder and subtracter is built using optoelectronic switch technologies in conjunction with fiber-multistage 3-D optoelectronic interconnects, Thus an effective combination of a parallel algorithm and a parallel architecture is implemented. In addition, the performance of the optoelectronic switches used in this system is experimentally studied and verified. Both the 3-bit experimental model and the experimental results of a parallel addition and a parallel subtraction are provided and discussed. Finally, the speed ratio between the MSD adder and binary adders is discussed and the advantage of the MSD in operating speed is demonstrated. (C) 1996 Society of Photo-Optical instrumentation Engineers.
收录类别	SCI
语种	英语
文献类型	期刊论文
条目标识符	http://ir.ciomp.ac.cn/handle/181722/25430
专题	中科院长春光机所知识产出
推荐引用方式 GB/T 7714	Sun D. G.,Wang N. X.,He L. M.,et al. Demonstration of an optoelectronic interconnect architecture for a parallel modified signed-digit adder and subtracter[J]. Optical Engineering,1996,35(6):1785-1793.
APA	Sun D. G.,Wang N. X.,He L. M.,Weng Z. H.,Wang D. H.,&Chen R. T..(1996).Demonstration of an optoelectronic interconnect architecture for a parallel modified signed-digit adder and subtracter.Optical Engineering,35(6),1785-1793.
MLA	Sun D. G.,et al."Demonstration of an optoelectronic interconnect architecture for a parallel modified signed-digit adder and subtracter".Optical Engineering 35.6(1996):1785-1793.

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